`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   12:23:56 07/09/2015
// Design Name:   MemoriaInstruccionesB
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/MemInstBTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MemoriaInstruccionesB
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module MemInstBTest;

	// Inputs
	reg clk;
	reg [31:0] addr;

	// Outputs
	wire [31:0] inst;

	// Instantiate the Unit Under Test (UUT)
	MemoriaInstruccionesB uut (
		.clk(clk), 
		.addr(addr), 
		.inst(inst)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		addr = 0;

		// Wait 100 ns for global reset to finish
		#100;
      addr = 1;
		#100;
		addr = 0;

	end
	
always begin
#1; clk = ~clk;
end
     
endmodule

